DK-DEV-5SGXEA7N【PDF 169/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51007

2014.01.10

Pin Placement Guidelines for DPA Differential Channels

6-13

Figure 6-7: LVDS Interface with the Altera_PLL Megafunction (With Soft-CDR Mode)

This figure shows the connections between the Altera_PLL and ALTLVDS megafunction if you are using

soft-CDR mode. The locked output port must be inverted and connected to the pll_areset port.

FPGA Fabric

LVDS Transmitter

Transmitter

Core Logic

D

Q

(ALTLVDS)

tx_in tx_inclock

tx_coreclk

tx_enable

outclk0

Altera_PLL

outclk1

outclk2

outclk3

inclk0

rx_coreclk

LVDS Receiver

(ALTLVDS)

locked

pll_areset

Receiver

Core Logic

Q

D

rx_out

rx_divfwdclk

rx_inclock

rx_dpaclock

rx_enable

rx_syncclock

pll_areset

When generating the Altera_PLL megafunction, the Left/Right PLL option is configured to set up the PLL

in LVDS mode. Instantiation of pll_areset is optional.

The rx_syncclock port is automatically enabled in an LVDS receiver in external PLL mode. The Quartus II

compiler output error messages if this port is not connected as shown in the preceding figures.

Pin Placement Guidelines for DPA Differential Channels

DPA usage adds some constraints on the placement of high-speed differential channels. If DPA-enabled or

DPA-disabled differential channels (9) in the differential banks are used, you must adhere to the differential

pin placement guidelines to ensure the proper high-speed operation. The Quartus II compiler automatically

checks the design and issues an error message if the guidelines are not followed.

Note: The figures in this section show guidelines for using corner and center PLLs but do not necessarily

represent the exact locations of the high-speed LVDS I/O banks.

Related Information

Guideline: Use PLLs in Integer PLL Mode for LVDS on page 6-8

Guideline: Using DPA-Enabled Differential Channels

Each differential receiver in an I/O block has a dedicated DPA circuit to align the phase of the clock to the

data phase of its associated channel. If you enable a DPA channel in a bank, you can use both single-ended

I/Os and differential I/O standards in the bank.

You can place double data rate I/O (DDIO) output pins within I/O modules that have the same pad group

number as a SERDES differential channel. However, you cannot place SDR I/O output pins within I/O

modules that have the same pad group number as a receiver SERDES differential channel. You must

implement the input register within the FPGA fabric logic.

If you use DPA-enabled channels in differential banks, adhere to the following guidelines.

(9)

DPA-enabled differential channels refer to DPA mode or soft-CDR mode while DPA disabled channels refer

to non-DPA mode.

High-Speed Differential I/O Interfaces and DPA in Stratix V Devices

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